The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for tracking effective addresses in an out-of-order processor.
Most modern computing devices provide support for the concept of virtual memory. Virtual memory is a technique by which application programs are given the impression that they have a contiguous working memory, or address space, when in fact the physical memory may be fragmented and may even overflow onto disk storage. Essentially, the application program is given a view of the memory of the computing device where the application accesses a seemingly contiguous memory using an effective address, in the effective address space visible to the application, which is then translated into a physical address of the actual physical memory or storage device(s) to actually perform the access operation. An effective address is the value which is used to specify a memory location that is to be accessed by the operation from the perspective of the entity, e.g., application, process, thread, interrupt handler, kernel component, etc., issuing the operation.
That is, if a computing device does not support the concept of virtual memory, then the effective address and the physical address are one and the same. However, if the computing device does support virtual memory, then the effective address of the particular operation submitted by the application is translated by the computing device's memory mapping unit into a physical address which specifies the location in the physical memory or storage device(s) where the operation is to be performed.
In modern computing devices, the processors of these computing devices use processor instruction pipelines, comprising a series of data processing elements, to process instructions (operations) submitted by entities, e.g., applications, processes, etc. Instruction pipelining is a technique to increase instruction throughput by splitting the processing of computer instructions into a series of steps with storage at the end of each step. This allows the computing device's control circuitry to issue instructions to the processor instruction pipeline at the processing rate of the slowest step which is much faster than the time needed to perform all steps at once. Processors with instruction pipelining, i.e. pipelined processors, are internally organized into stages which can semi-independently work on separate jobs. Each stage is organized and linked with a next stage in a series chain so that each stage's output is fed to another stage until the final stage of the pipeline.
Such pipelined processors may take the form of in-order or out-of-order pipelined processors. For in-order pipelined processors, instructions are executed in order such that if data is not available for the instruction to be processed at a particular stage of the pipeline, execution of instructions through the pipeline may be stalled until the data is available. Out-of-order pipelined processors, on the other hand, allow the processor to avoid stalls that occur when the data needed to perform an operation are unavailable. The out-of-order processor instruction pipeline avoids these stalls by filling in “slots” in time with other instructions that are ready to be processed and then re-ordering the results at the end of the pipeline to make it appear that the instructions were processed in-order. The way the instructions are ordered in the original computer code is known as program order, whereas in the processor they are handled in data order, i.e. the order in which the data and operands become available in the processor's registers.